The present invention relates to an improved multilayer conductor for use with electrical circuits. Multilayer conductors constructed according to the invention may be used advantageously in field emission displays (FEDs) as well as in other integrated circuits.
Since a preferred use of the invention is in FEDs, the background of FEDs will now be discussed. FIG. 1A shows a cross sectional view of a portion of a prior art FED 100. FED 100 includes a cathode, or baseplate, 102 and an anode, or faceplate, 104. Baseplate 102 includes a substrate 106, a plurality of conical field emitters 108, a dielectric layer 110, and a conductive grid layer 112. Dielectric layer 110 is disposed over substrate 106, and grid layer 112 is disposed over dielectric layer 110. Dielectric layer 110 defines a plurality of cylindrical, or bowl shaped, void regions 114, and each emitter 108 is disposed over substrate 106 in one of the void regions 114. Grid layer 112 defines a plurality of circular apertures 116. Each aperture 116 corresponds to, and overlies, one of the void regions 114. A single emitter 108 is disposed underneath each of the apertures 116. The apertures 116 are positioned so that (1) the grid layer 112 does not obstruct a path 117 between the upper tips of the emitters 108 and the faceplate 104 and (2) a portion of the grid layer 112 is proximal to the upper tip of each emitter 108. Baseplate 102 also includes a plurality of conductive column lines 118 disposed between emitters 108 and substrate 106. In FIG. 1A, portions of three column lines are shown as lines 118a, 118b, and 118c. 
FIG. 1B shows a magnified top view of a portion of baseplate 102. The grid layer 112 is arranged as a set of conductive row lines (three of which 112a, 112b, 112c are shown) with the row lines being perpendicular to the underlying column lines 118.
Referring again to FIG. 1A, faceplate 104 includes a transparent glass plate 120, a transparent conductor 122, and a phosphor layer 124. Transparent conductor 122 is disposed on one major surface of glass plate 120, and phosphor layer 124 is disposed on transparent conductor 122. Faceplate 104 also includes a black matrix (not shown). The black matrix divides the phosphor layer into an array, or matrix, of pixels. The location of one of the pixels 160 is indicated in FIG. 1A. Pixel 160 could be a single pixel of a black and white display or alternatively could form a single red, green, or blue dot of a color (RGB) display. The faceplate 104 and baseplate 102 are spaced apart from one another and are disposed so that the phosphor layer 124 is proximal to the grid layer 112.
The collection of emitters 108 disposed at the intersection of a single row line and a single column line are used to control illumination of a single pixel of the display 100. For example, as shown in FIG. 1B, a group 162 of approximately sixteen emitters 108 (disposed within the approximately sixteen apertures 116) is located at the intersection of row line 112b (of the grid layer 112) and column line 118b. This group 162 of emitters is used to control illumination of pixel 160 (indicated in FIG. 1A). Typical displays often use hundreds or thousands of emitters to control illumination of a single pixel. However, for convenience of illustration, FIG. 1B shows only about sixteen emitters per pixel.
Referring again to FIG. 1A, FED 100 also includes a plurality of spacers 130 disposed between faceplate 104 and baseplate 102. The spacers 130 maintain the orientation between baseplate 102 and faceplate 104 so that the baseplate and faceplate are substantially parallel to one another. Outer walls (not shown) seal the outer periphery of FED 100 and the space between baseplate 102 and faceplate 104 is substantially evacuated (creating a vacuum of about 10xe2x88x927 Torr). Since the space between faceplate 104 and baseplate 102 is substantially evacuated, atmospheric pressure tends to press baseplate 102 and faceplate 104 together. Spacers 130 resist this pressure and maintain the substantially parallel, spaced apart, orientation of baseplate 102 and faceplate 104.
FED 100 also includes a power supply 140 for (1) charging the transparent conductor 122 to a highly positive voltage (e.g., 1,500 Volts); (2) selectively charging rows of the conductive grid layer 112 to a positive voltage (e.g., 30 Volts); and (3) selectively charging the conductive column lines 118 to a negative voltage (e.g., xe2x88x9210 Volts).
In operation, voltages applied to the column lines 118, the rows of the grid layer 112, and the transparent conductor 122 selectively cause emitters 108 to emit electrons 150 that travel along path 117 towards, and impact on, phosphor layer 124. Incident electrons on phosphor layer 124 cause phosphor layer 124 to emit photons and thereby generate a visible display on faceplate 104. Power supply 140 generates a visible display by periodically illuminating (or not illuminating) the pixels in the display matrix. Normally, power supply 140 continuously charges transparent conductor 122 to the highly positive voltage. Power supply 140 illuminates a single pixel by simultaneously applying the negative and positive voltages to that pixel""s column and row lines, respectively.
The column lines 118 and the rows of the grid layer 112 are typically made from strips of aluminum. Although aluminum has been used for many years to form conductors in FEDs as well as in other types of integrated circuits, aluminum has several undesirable characteristics. For example, aluminum is not physically stable over long periods of time when it is disposed adjacent to silicon-based materials. Aluminum has a tendency to slowly diffuse into adjacent silicon-based materials and form structures known as xe2x80x9chillocksxe2x80x9d. Since almost every layer of modern integrated circuits is silicon-based (e.g., silicon oxide, silicon nitride, single crystal silicon, polycrystalline silicon, or glass), the tendency of aluminum to diffuse into silicon-based layers is a serious drawback to its use. As used herein, the term xe2x80x9csilicon-basedxe2x80x9d shall mean any material that includes silicon, either in elemental form or in the form of one or more compounds.
FIGS. 2A, 2B, 2C, 2D illustrate the undesirable tendency of aluminum for forming hillocks in adjacent silicon-based layers. FIG. 2A shows a top view of a structure 200 and FIG. 2B shows a magnified sectional view of structure 200 taken in a direction indicated by line 2Bxe2x80x942B as shown in FIG. 2A. Structure 200 includes four conductive aluminum lines 210, 211, 212, 213 disposed between, and in physical contact with, a lower silicon-based layer 202 and an upper silicon-based layer 204. It will be appreciated that structure 200 could represent a small portion of almost any integrated circuit.
The lower silicon-based layer 202 could comprise a substrate made for example from single crystal silicon, polycrystalline silicon, or glass. More commonly, both upper and lower silicon-based layers 202, 204 would be silicon-based insulators made for example from silicon oxide or silicon nitride. In this case, additional layers (e.g., silicon-based layers containing active devices such as transistors) could be disposed both above and below the upper and lower silicon-based layers 202, 204. It will be further appreciated that aluminum lines 210-213 could comprise a small portion of a bus (e.g., an address bus or a data bus) in a memory or processor chip. Alternatively, aluminum lines 210-213 could comprise a portion of the column lines in a FED. In that case, lower silicon-based layer 202 would be part of the baseplate 102 (as shown in FIG. 1A). In typical applications the width W of the conductive lines is about 2,000 Angstroms and the thickness T of the conductive lines is about 1,000 to 2,000 Angstroms. Although the illustrated aluminum lines are xe2x80x9cstraight linesxe2x80x9d, it should be appreciated that conductive xe2x80x9clinesxe2x80x9d in integrated circuits are typically not straight and instead include several line segments or arcs connected by right angles or other angles. The term xe2x80x9clinexe2x80x9d as used herein refers to a conductor that extends along any path between two points.
FIGS. 2C and 2D show top and magnified sectional side views, respectively, of structure 200 after some of the aluminum from line 211 has diffused into the lower silicon-based layer 202 and formed a hillock 211A. The hillock 211A is a xe2x80x9cthreadxe2x80x9d or xe2x80x9cspikexe2x80x9dof aluminum that has diffused from its original location (over lower silicon-based layer 202) into silicon-based layer 202. Typically, formation of the hillock 211A will increase the electrical resistance of the line 211 and thereby degrade the performance of structure 200. Also, if enough aluminum from the line diffuses into the hillock, formation of the hillock can cause a xe2x80x9cbreakxe2x80x9d or an xe2x80x9copen circuitxe2x80x9d to form in the aluminum line. Sometimes hillocks extend towards adjacent conductive lines and can result in electrically connecting two previously unconnected lines.
Typically, aluminum diffuses rather slowly into adjacent silicon-based layers and it normally takes several years to form hillocks of appreciable size. However, this diffusion process is not well understood and hillocks sometimes form much faster.
Another problem with aluminum is that it suffers from a phenomenon known as xe2x80x9celectromigrationxe2x80x9d. In some materials, conduction of electric current can cause permanent physical movement of the material, and this movement is called xe2x80x9celectromigrationxe2x80x9d. Typically, the amount of electromigration experienced by a material is somewhat proportional to the amount of electric current conducted by the material. So electromigration is a more serious problem for high current devices such as FEDs than it is for low current devices such as logic gates. Aluminum typically experiences some degree of electromigration regardless of where the aluminum is disposed. However, when aluminum is disposed in physical contact with a silicon-based material (e.g., as in a typical integrated circuit application), the tendency of aluminum to experience electromigration exacerbates the above-discussed tendency for aluminum to form hillocks.
Yet another problem with aluminum relates aluminum""s susceptibility to corrosion by etchants typically used in fabrication of integrated circuit devices. For example, aluminum is susceptible to corrosion by hydrogen-fluoride-based etchants (e.g., such as the etchants used in xe2x80x9cbuffered oxide etchesxe2x80x9d) and by sulfuric-acid-based etchants such as Piranha(trademark), both of which are used to etch the dielectric layer in FEDs. Since aluminum is susceptible to corrosion by these etchants, it can be difficult to form other features in electronic devices (e.g., the dielectric layer in an FED) without simultaneously damaging aluminum lines.
One known technique for addressing these problems with aluminum is to dope the aluminum lines with various dopants (e.g., 4 wt % Copper and 1.7 wt % Silicon). One problem with this technique is that doping an aluminum line tends to raise the per-unit-length electrical resistance of the line.
It would therefore be advantageous to develop other solutions to the problems with aluminum.
The invention is directed to an improved multilayer conductor. Multilayer conductors constructed according to the invention provide absolution to the above-discussed problems associated with using aluminum lines as conductors in integrated circuits. In a typical embodiment, a multilayer conductor constructed according to the invention includes a line of aluminum (or another highly conductive material) disposed between two lines of chromium (or between two lines of another physically stable conductive material). When the multilayer conductor is used in an integrated circuit, the two lines of chromium shield the aluminum line from physical contact with adjacent silicon-based layers.
Chromium tends to be physically stable when disposed in physical contact with silicon-based materials. More specifically, chromium does not tend to diffuse into adjacent silicon-based materials and form hillocks and chromium does not suffer appreciably from electromigration. Also, chromium and aluminum are physically stable when they are disposed in physical contact with one another. In essence, the chromium forms a protective shield around the aluminum that preserves the original geometric configuration of the aluminum line over very long periods of time.
Another advantage of chromium is that it is more resistant than aluminum to corrosion by etchants (e.g., hydrogen-fluoride-based etchants or sulfuric-acid based etchants) commonly used in fabrication of integrated circuits. So, chromium tends to protect the integrity of multilayer conductors constructed according to the invention during integrated circuit fabrication processes.
The electrical resistance of chromium is higher than that of aluminum. However, chromium is an electrical conductor, so if an unintended break does develop in an aluminum line of a multilayer conductor constructed according to the invention (e.g., as a result of a flaw in the fabrication process), the chromium lines can provide a conductive bridge around the break. The multilayer conductor of the invention therefore provides improved reliability and an increased tolerance for fabrication flaws. Also, even though the electrical resistance of chromium is higher than that of aluminum, the electrical resistance provided between any two points of a multilayer conductor constructed according to the invention can be controlled by appropriately selecting the dimensions of the aluminum and chromium lines. In general, the electrical resistance of a multilayer conductor constructed according to the invention can be reduced by increasing the dimensions, or cross-sectional area, of the aluminum and chromium lines used to form the conductor.
Multilayer conductors constructed according to the invention can be advantageously substituted for aluminum conductors in almost any integrated circuit. For example, multilayer conductors can be used as conductors in memory chips, processor chips, amplifiers, linear circuits, logic circuits, or FEDs.
As discussed above, the preferred embodiment of the multilayer conductor includes an aluminum line disposed between two chromium lines. More generally, multilayer conductors constructed according to the invention include a primary conductive layer disposed between two protective layers. Although the most common material for use as the primary conductive layer is aluminum, other materials such as aluminum containing alloys, copper, copper containing alloys, or other alloys could be used. Also, while chromium is the most preferred choice for the protective layer, other materials such as chromium containing alloys or tungsten could be used.
Whereas prior art integrated circuits have used conductive lines fabricated from a single layer of metal (e.g., a layer of aluminum or copper), the invention provides a conductor that is fabricated from at least two distinct layers of different materials (e.g., one layer of aluminum and another layer of chromium). As discussed herein, forming conductors from two distinct layers of different materials provides significant advantages.
The preferred embodiment of the invention is a multilayer conductor that includes one primary conductive line disposed between two adjacent protective lines. However, other embodiments could include only a single protective line (e.g., for applications in which only one side of the multilayer conductor is in physical contact with a silicon-based material). Still other embodiments could include more than three layers. For example, a multilayer conductor constructed according to the invention could include two primary conductive lines and three protective lines. One of the protective lines separates the two primary conductive lines and the other two protective lines are disposed on the top and bottom of the multilayer conductor.
Still other objects and advantages of the present invention will become readily apparent from the following detailed description wherein several embodiments are shown and described, simply by way of illustration of the best mode of the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not in a restrictive or limiting sense, with the scope of the application being indicated in the claims.